1. Technical Field
Apparatuses and methods consistent with exemplary embodiments relate generally to integrated circuits, and more particularly to a memory device for adaptively calibrating a timing margin and an integrated circuit including the memory device.
2. Discussion of the Related Art
Recently, many integrated circuits have adopted a dynamic voltage and frequency scaling (DVFS) scheme for low-power operations. To enhance a performance of an embedded memory such as a static random access memory (SRAM) included in the integrated circuit, a timing margin or an operation timing must be adjusted according to a change of an operating voltage or a driving voltage. In some related art schemes, if the integrated circuit has simple clock domains or power domains, a clock signal may be stopped to prevent operation errors while the operating voltage and the timing margin are changed. However, when the integrated circuit has complex clock domains using many clock signals, such a clock-stop scheme may cause performance degradation of the integrated circuit.